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VLAN implementation using NS2

Modeling Multiprocessor Systems


  • Synchronous Data Flow Graph (SDFG)
    The Synchronous DFG is similar to a directed graph which contains vertices and edges. Where each vertex represents the computation and the edges do the job of carrying the data from one vertex to another
    Vertex is represented by a circle whereas the edge is denoted as an arrow.


  • Homogeneous Synchronous DFG (HSDFG)
    When there is only one token at the input and only one token at the output in a SDFG, then it is said to be Homogeneous Synchronous DFG (HSDFG). Usually SDFG is converted into a HSDFG by making the input and output to have one token, so that there will be lot of small HSDFG created out of SDFG.


  • Acrylic Precedence Expansion Group (APEG)
    APEG is obtained by removing the delay elements from the SDFG. Each vertex takes inputs and giving outputs, if any such inputs contains delay, then the delay has to be removed to obtain the Acrylic Precedence Expansion Group (APEG)

Example for all the above models is given below · The above figure shows the Directed Graph which includes two instructions X and Y which belongs to Processor A (PA) and processor B (PB) respectively.
· The outputs from X are (a, b, c) and two of its outputs are sent to Y as inputs. There are two other inputs i, j are sent to Y. so the total inputs to Y is 4. This is indicated by a circle with 4 as the number of inputs. So this graph is said to be SDFG.
· To convert this in to HSDFG, there should be only one token at the input and output.
· In the above figure, there are two inputs to Y and it is being separated as one input, one from X1 and another from X2. (X1 & Y) makes one HSDFG and (X2 & Y) makes another HSDFG.
· APEG is obtained from removing the delay elements from an HSDFG. In the above figure there is no delay element between (X2 and Y), but there is a delay between (X1 and Y).
· So the following figure is APEG


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