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Showing posts from August, 2008

Installing ns-3.37 and ns-3.35 in Ubuntu | Ubuntu 22.04 | NS3

Multiple Versions of ns3 in Ubuntu 22.04 In this post, we are going to install two versions of ns3 namely ns-3.35 and ns-3.37  My OS is : Ubuntu 22.04 LTS (Long Term Support) ns-3.35 uses waf and (./waf --run scratch/first)  ns-3.37 uses cmake  (./ns3 run scratch/ So we will install both the packages  Go through the video for complete instructions To start with  $ sudo apt update  $ sudo apt install build-essential autoconf automake libxmu-dev g++ python3 python3-dev pkg-config sqlite3 cmake python3-setuptools git qtbase5-dev qtchooser qt5-qmake qtbase5-dev-tools gir1.2-goocanvas-2.0 python3-gi python3-gi-cairo python3-pygraphviz gir1.2-gtk-3.0 ipython3 openmpi-bin openmpi-common openmpi-doc libopenmpi-dev autoconf cvs bzr unrar gsl-bin libgsl-dev libgslcblas0 wireshark tcpdump sqlite sqlite3 libsqlite3-dev  libxml2 libxml2-dev libc6-dev libc6-dev-i386 libclang-dev llvm-dev automake python3-pip libxml2 libxml2-dev libboost-all-dev  I have downloaded both the versions of ns3 fr

Modeling Multiprocessor Systems

Synchronous Data Flow Graph (SDFG) The Synchronous DFG is similar to a directed graph which contains vertices and edges. Where each vertex represents the computation and the edges do the job of carrying the data from one vertex to another Vertex is represented by a circle whereas the edge is denoted as an arrow. H omogeneous Synchronous DFG (HSDFG) When there is only one token at the input and only one token at the output in a SDFG, then it is said to be Homogeneous Synchronous DFG (HSDFG). Usually SDFG is converted into a HSDFG by making the input and output to have one token, so that there will be lot of small HSDFG created out of SDFG. Acrylic Precedence Expansion Group (APEG) APEG is obtained by removing the delay elements from the SDFG. Each vertex takes inputs and giving outputs, if any such inputs contains delay, then the delay has to be removed to obtain the Acrylic Precedence Expansion Group (APEG) Example for all the above models is given below · The above figure shows the D

Petri Net Model

· It is a powerful tool for Real Time Embedded systems · It is a graphical modeling tool suggested by C A Petri · Used in designing the algorithms for control circuits, computational and communication operators · FSM is used when there are finite number of states and petri nets are used when the number of states is definite · Instead of the states of the FSM model, there are the node-places and node-Transitions at each net. · A circle shows the Node-places and a rectangle shows the Node-Transition. · The node-place describes the state and the Node Transition describes the computations and Actions · Each entry point or initial node place is indicated by a dot in the centre of the node place and is called the masking place. Timer Using Petri Net

Finite State Machines (FSM) Models

Examples include: · Telephone with states – idle, receiving a ring, dialing, connected · Washing Machine with states – washing, rinsing, drying · Timers with states- idle, start, running 1) Inputs to the process changes the state to a new state. The process change from one state to another state is called as transition 2) A state can receive multiple tokens (inputs, messages, interrupt flags, semaphores, etc). A token means either an input or event input. 3) Event input is asynchronous, Eg. Semaphore taken or released, completion of execution of set of codes. 4) A state can similarly generate multiple tokens. FSM for a Timer FSM of an Interrupt Service Routine There are 5 states namely – Idle, Call, running, blocked, return

Program Modelling Concepts

Modelling Processes for Software Analysis before Software Implementation Data Flow Graph (DFG) Data Flow Graph (DFG) as the name says only the data which is flowing in to a process taken into account. for example going to a bank for depositing the cash includes the data 1) input is account number and 2) output data is balance in the account. Other examples: Finding the average marks scored by a student: the input data is grades or marks scored and output data is the average grades or marks. the process is the (sum/total number of subjects). usually the input data is fed in to a process and output data comes after processing the input data. DFG does not have any conditions within it, but has only data entry point and one data output entry point. When there is only one set of values of each of the inputs and only one set of values of the outputs for the given input, a DFG is also known to be Acrylic Data Flow Graph (ADFG) Example of ADFG: In an FIR Filter with y6=a0x6+a1x5+......+a6x0,

Interrupt Servicing (Handling) Mechanism

Sources of Interrupts Software Error Related Sources: Overflow Underflow Division by zero Illegal opcode Programmer defined exceptions Software code related sources Breakpoint Debugging trap RTC driven software timer Input driven software timer Semaphore take and release Even related Task blocking overflow Task finished timeouts Internal Hardware device sources Parallel port and UART serial receiver port UART transmission complete ADC Start of conversion and End of Conversion Pulse Accumulator Real Time Clock Watch Dog Timer Reset Timer overflow on timeouts External Hardware with internal vector address Maskable pin Non Maskable pin External Hardware with external Vector Address INTR (Interrupt Request pin of 80x86 Context Switching Context A context of a program includes program counter and stack pointer. But in some special cases, the context also includes status word register and processor registers. Context saving and restoring Pushing all the register at the beginning of an int

Device Driving ISRs in a System

Writing Device Driving ISRs in a System A device has three sets of device registers Data Register Control Register Status register A device initializes by setting the control register bit and the device closes b y resetting the control register bits. There may be more than one device register at a device address. Control register bits controls all the action of the device. Status register bits reflects flags for the status of the device at an instant and changes after performing the actions as per device driver ISRs can be called either by setting the status flag or a hardware call by a signal to initiate. The status and control registers should be available at the same address, since the processor reads the status from the address during read operation and writes at the same address during the write operation. Parallel Port Device driver in a System Step A – Device Initialisation Program Step B – Device Driver Program Step 0, 1, 2, 3, 4, 5 – Interrupt Service Routine for PORTA. Seri

Device Driving ISRs

1. A device has 3 set of registers Data Register Control Register (controls all actions of the device) Status Register (reflects the flags for the status of the device at an instant and changes after performing the actions as per device drivers) 2. A device initializes by setting the control register bit and the device closes by resetting the control register bits. 3. Both the status and control register bits will be in the same address space,as the processor reads the status from this address during read operation and writes during the write operation. 4. ISRs can be called either by setting the status flag or a hardware call by a signal to initiate.