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Showing posts from July, 2008

Other High Speed Buses

ISA (IBM Standard Architecture) connects only to a card that has an 8-86,186 or 286 processor, and in which the processor addressing and IBM PC architecture addressing limitations. ISA Bus memory in two ranges: 640kb to 1MB or 15MB to 16MB . The instruction set provides 64k I/O, the ISA ignores A10 to A15 addresses and therefore only 1024 I/O port addresses are available. EISA (Extended ISA) works for 32 bit data and address lines version of ISA. PCI and PCI-X Buses Peripheral Component Interconnect Platform Independent (Connects to any architecture and not like ISA) PCI provides three types of synchronous parallel interfaces a) 32/33 MHz b) 64/66MHz and PCI-X supports 64/100MHz Later two super speed versions of PCI have been introduced PCI Super - 264/528 MBps at 3.3V on a 64 bit bus PCI Super - 132/264 Mbps on a 32 bit bus PCI-X Super - 800 MBps on a 64 bit bus at 3.3V

CAN (Controller Area Networks)

Is a high-integrity serial data communications bus for real-time control applications Operates at data rates of up to 1 Mega bits per second Was originally developed for use in cars, Is now being used in many other industrial automation and control applications Fields in a CAN Frame A Standard CAN Frame consists of seven different bit fields: A Start of Frame (SOF) field - which indicates the beginning of a message frame. An Arbitration field, containing a message identifier and the Remote Transmission Request (RTR) bit. The RTR bit is used to discriminate between a transmitted Data Frame and a request for data from a remote node. A Control Field containing six bits: * two reserved bits (r0 and r1) and * a four bit Data Length Code (DLC). The DLC indicates the number of bytes in the Data Field that follows A Data Field, containing from zero to eight bytes. The CRC field, containing a fifteen bit cyclic redundancy check code and a recessive delimiter bit The ACKnowledge field, consi

USB (Universal Serial Bus)

USB is a device that can be attached, configured and used, reset, reconfigured and used, share the bandwidth with other devices, detached (while others are in operation) and reattached Developed by Intel, Microsoft and Philips in 1998.Initial model was USB 1.0. The latest version is USB 2.0. Currently supported versions are USB 1.1 and 2.0 The Speed of USB 1.1 is(1.5Mbps or 12 Mbps) The speed of USB 2.0 is 480Mbps. USBs are bus powered or self powered. USBs are hot pluggable (once they are installed, there is no need for rebooting the system). USBs share their bandwidth. 127 USB devices can be connected to a single USB slot and all the devices shares the bandwidth. USBs has four wires, one for +5v, one for ground and two for twisted pair cables. The next version under research is USB3.0, the speed of it may be around 4.8Gbps.

Timers

Timers Timers are there to count the internal clock Pulses of a Micro controller. Counters are there to count the external pulses. States of a Timer Reset Initial State Running Blocked Finished Overflow Uses of a Timer Event driven(initiate an event after a delay) Scheduling of Tasks in a System (by activating and running a timer) Watchdog Timer (Resets the system after a predefine time) Real Time clock (A clock that never stops and keeps on running and never be reset, Eg. Heart Beat) Time slicing of various tasks. There are two types of timer Hardware Timer Atleast one hardware should be available in a Microcontroller. The figure above shows the Hardware Timer has the control bits Timer Enable Timer Start Timer Stop Pre scaling bits Up count enable Down count disable Load Enable Timer Interrupt Enable

IO Devices (Input Output Devices)

Some Examples of IO Devices Serial Input devices: Audio/video input, dial tone in a telephone Serial Output Devices : Audio/Video Output, Dialing a Number Serial UART Input: Modem, Keyboard, Keypad, Mouse Serial UART Output: Modem, printer Parallel Port Single bit input: Filling a liquid up to a fixed level Parallel Port Single bit output: Pulses to an External Circuit Parallel port Input: Encoder inputs for bits for angular position of a shaft Parallel Port Output: Printer driving output bits Serial Device Serial Devices operates in three modes Synchronous When a byte or frame is transmitted at a constant time interval with uniform phase difference, then the transmission is said to be synchronous Examples: Frames sent over a Local Area network. Asynchronous Here byte or frame is transmitted at random time intervals Iso-synchronous It is a special case where the max time interval can be varied

Direct Memory Access

Memory Map Harvard Architecture Von Newman Architecture Direct Memory Access (DMA) DMA is a circuit that can read data from an I/O Device and then write it into memory. In general, the IO Devices accessing the Memory with least bothering the processor. The IO Devices request the DMAREQ and then the DMA Controller requests the BUSREQ from the processor. Once the processor gives back the BUSACK, the IO Device is ready to write to the memory or read from the memory. During the initiation of the BUSACK from the Processor, the Processor also places the Address on to which the data is to be written to the memory. Most of modern high end controllers or processors will be having the DMA controller in built in it.

Memory

Design the system with its Block Diagram and processor selection

Submission Date: 5th August 2008 Temperature Controller in a Nuclear Reactor 05BCE187, 223, 229, 219, 193, 04BCE127 (D Sec) 1st Batch - 05BCE133, 155, 145, 153, 130 (C Sec) 2nd Batch - 05BCe159, 158, 152, 146, 179, 167 (C Sec) Adaptive Cruise Control 1st Batch - 05BCE180, 190, 185, 206, 230 (D Sec) 2nd Batch - 05BCE213, 227, 216, 183, 211, 214 (D Sec) 1st Batch - 05BCE124, 128, 129, 134, 160, 161 (C Sec) 2nd Batch - 05BCE125, 140, 141, 142, 175, 178 (C Sec) Design of ATM System 1st Batch - 05BCE204 , 220, 195, 200, 212, 221 (D Sec) 2nd Batch - 05bce188, 194, 197, 201, 199, 203 (D Sec) Chocolate Vending Machine 1st Batch - 05BCE181, 209, 202, 217 (D Sec) 2nd Batch - 05BCE215, 205, 210, 182, 226 (D Sec) 1st Batch - 05BCE126, 127, 135, 136, 137 (C Sec) Embedded TCP/IP 05BCE207, 218, 232, 191, 228 (D Sec) Mobile Phone 05BCE192, 186, 222, 196, 224, 208 (D Sec) 05BCE139, 147, 148, 157, 143 (C Sec) Real Time Video Processing 04BCE193, 186, 109, 046, 102, 084 (D Sec) 05BCE156, 172, 154, 1

Processor Design in an Embedded Systems

The following are the units of the processor IR - Instruction Register - Takes the Instruction codes to the Execution Unit IQ - Instruction Queue - Queue of Instructions so that the IR does not have to wait for Next Instruction ID - Instruction Decoder - It Decoded the opcode and sent it to CPU CU - Control Unit - It control the Internal buses and other functionalities ALU - Arithmetic and Logic Unit SRS - System Register Set - Register set to store the system program ARS - Application Register Set - Set of on chip register used during the processing of application program of the user SP - Stack Pointer - Points to the address of the top of the stack MAR - Memory Address Register - It holds the address of the data from an external memory MDR - Memory Data Register - It holds the data from an external memory (either it will read from the memory or write to the memory) PC - Program Counter - It contains the next instruction to be executed. BIU - Bus Interface unit - It interfaces be

SoC (System on Chip Controllers)

Soc Contains Multiple Processors (Digital Signal Processors may also be included) Memories (which contributes to nearly 60% of the total Size of the chip) IP Cores (Intellectual Property Cores) - Apart from gates, counter, register, FPU and ALU, a standard solution for synthesizing a higher level component by configuring FPGA core may be available as an IP Core. The copyright for the synthesized design is held by the designer or by the designing company. Logic and Analog Circuits DMA Controllers (DMAC) Interrupt Controller Network Protocol Encryption And Decryption Unit FPGA Cores, etc

Software tools for Embedded Systems

Final Machine Implementable Software Its like a table of address and bytes at each address of the system memory The table has to read as a ROM image for the targeted hardware. bytes are allocated for Stack Space, Startup code, ISRs, Kernels,etc If the system is updated, then the storage of bytes in the System ROM image also to be changed or updated. Software for a Processor Specific Assembly Language This technique is widely used now a days, in which the programmer should aware of the processor specfic assmebly language to program Cross Assembler is one which creates object code for a target architecture in which the input is the assembly language Cross Compiler is one which creates object code for a different target architecture in which the input is a high level language Linker is an entity in which the linking files or libraries which are required to execute a program are linked during the runtime. Loader loads the program from the secondary memory to main memory. Locator also calle